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On Intel’s Xeon Scalable Roadmap, E-Core Xeons will be introduced in 2024.

We all know that recent generations have seen a significant expansion of Intel’s enterprise CPU platform. For its multi-die plan, Intel is depending on a manufacturing platform that hasn’t delivered the best results yet compared to its competitors’. On the other hand, Intel is forecasting more Xeon products shipped in December than AMD shipped in the whole of 2021, and the company is launching a new Sapphire Rapids Xeon Scalable platform in 2022. Intel has been keeping its plans for the future of its processors under wraps, but today they’ve unveiled the whole scope of what they’ve been working on.

Today’s Situation:

Intel’s Ice Lake 3rd Generation Xeon Scalable Platform, based on Intel’s 10nm technology node and featuring up to 40 Sunny Cove cores, is now available on the market from Intel. Our benchmarks showed a significant generational increase in performance relative to the 2nd Generation Xeon product, which is 660 mm2. Intel’s Ice Lake Xeon processors have received mixed reviews in the market, but the company has pushed ahead with a more complete platform that includes FPGAs, memory storage, and networking, as well as unique accelerators. Depending on the quarter you look at, datacenter revenues can either rise or fall, depending on how processor stocks are being consumed by clients (as stated by CEO Pat Gelsinger).

On the other hand, the Sapphire Rapids 4th Generation Xeon Scalable platform has received a lot of attention from Intel. For example, we already know that Intel’s embedded bridge technology will be used to connect four tiles with more than 1600 mm2 of silicon for the highest core count options. Most of CXL 1.1 will be supported by the chip’s eight 64-bit DDR5 channels. Other enhancements to the Alder Lake desktop platform include new matrix extensions, data streaming accelerators, and rapid assist technology, all built on the newest P-core designs but tailored for datacenter use (which typically means AVX512 support and bigger caches). For the first time, the Aurora supercomputer at Argonne National Labs will be using HBM-enabled Sapphire Rapids, which will be paired with the new Ponte Vecchio high-performance compute accelerator.

It has taken longer than expected, but we expect Sapphire Rapids, which is based on Intel’s 7th process node technology, will be generally accessible in 2022.

Next-Generation Xeon Scalable Processors:

Intel is now releasing information to the general public to demonstrate what is to come on the company’s product roadmap beyond Sapphire Rapids. In 2023, we will have an Emerald Rapids Xeon Scalable product that is platform compatible with Sapphire Rapids and is also built on Intel 7. Based on the naming standards, Emerald Rapids is probably the 5th generation.

As with various other platform improvements, Emerald Rapids (EMR) is planned to make use of low-hanging fruit from the Sapphire Rapids design as well as manufacturing updates. In terms of PCIe lanes, CPU-to-PCIe connectivity, DRAM, CXL, and other IO capabilities being supported, Emerald is platform-compliant. We might expect to see new accelerators as well. In terms of what the silicon will look like, that’s still up for debate. Because we’re still relatively new to Intel’s tiling product lineup, there’s a strong chance it will be similar to Sapphire Rapids, but there might also be something entirely different, such as what Intel has in store for the generation following this one.

It is after Emerald Rapids when Intel’s road blueprint changes course and becomes a different route altogether. Intel’s strategy is going to be more diverse in the future.

At the top of the heap is Granite Rapids (GNR), which will debut in 2024 on an Intel 3 process node and be made completely of Intel’s performance cores. We had previously seen Granite Rapids on Intel’s roadmaps as a 4 node product, but Intel has informed us that this is no longer the case due to the advancement of the technology and the timescale in which it will be implemented. Because we expect the design guidelines to be quite similar between Intel 3 and Intel 4, which is intended to be Intel’s second-generation EUV node, we don’t foresee much of a change.

It will be a tiled architecture like Sapphire Rapids, but it will also feature a split strategy in its tiles: separate IO tiles and core tiles, rather than a unified design like that. It’s not clear how they’ll be connected, but the idea is that the IO tiles can house all the memory channels, PCIe lanes, and other features while the core tiles may be optimised just for speed. Despite the fact that it sounds like Intel’s rivals are doing the same thing, it’s the correct thing to do.

Sierra Forest (SRF) and Granite Rapids (GR) are the first two products in Intel’s new product range, which is based on Intel 3.0. Intel’s Alder Lake E-cores will be used in this new product line, which will be based on datacenter-optimized E-cores. We’ll see a new generation of E-cores in Sierra Forest, but the goal here is to deliver a product that focuses more on core density than on core performance itself. If the memory bandwidth and connectivity can keep up, they can run at lower voltages and parallelize.

Granite Rapids’ IO die will be used for Sierra Forest. Assuming they are socket compatible, we can expect the same DDR and PCIe settings for both systems because they will share a common platform. If Intel’s current numbering scheme is maintained, the products GNR and SRF will be referred to as such if Intel’s current numbering scheme is maintained. According to Intel’s briefing, the Ice Lake Xeon product line will be supplemented with a mix of GNR and SRF Xeons depending on client needs. SRF and GNR are intended to be available in every country when they are released.

A comparison between the E-core Sierra Forest’s concentration on core density and that of AMD’s Bergamo, which is expected to be termed Zen4c’s Bergamo for SRF, will be inevitable.

My question to Intel was whether or not the change to GNR+SRF on one unified platform meant that the following generation would be a unique platform or whether or not it would maintain the two-generation retention that customers prefer. I was told that it would be ideal to maintain platform compatibility across generations as they are planned; however, timing and where new technologies need to be included are factors in this decision.Even though PCIe 6.0 and DDR6 aren’t expected until 2026 and 2030, it’s likely that 6th and 7th Gen Xeon processors will be on par with each other in terms of performance.

If Intel is now making P-core tiles and E-core tiles, what’s keeping them from making a combination product with both? Unicore designs are preferred in this industry since the needs of each customer are different. An 80/20 split between P-and E-core customers is preferred by one, whereas a 20/80 split is preferred by another. Many separate items for each different ratio doesn’t make sense, and customers who are already researching this are finding that the software performs better with a uniform design rather than split at the socket level. So hybrid Xeons aren’t going to happen anytime soon. (Ian: That’s great news.)

It was my intention to inquire about the unified IO die, which might not be ideal for both P-core alone and E-core only Xeons. With the exception of the fact that integrating them both into the same platform allowed customers to synergize non-returnable development expenses across both CPUs, Intel didn’t have a strong answer to this. It’s possible that we may see additional Xeon-D-like scenarios with alternative IO configurations for smaller installations, but we’re talking about devices that are at least 2-3 years away at this moment.

Granite Rapids and Sierra Forest: Intel is already working with “definition customers” on the development, testing, and deployment of microarchitecture and platforms for Granite Rapids and Sierra Forest. More information will be forthcoming, particularly as we proceed through the Sapphire and Emerald Rapids in the coming year and the following year.